IEEE

Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond

Abstract: The implementation of vertically stacked gate-all-around nanosheet FET (GAA NSFET) may help improve the performance of static random access memory (SRAM) for the design flexibility with ...
IEEE

A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

Abstract: As minimum area SRAM bit-cells are obtained when using cell ratio and pull-up ratio of 1, we analyze the possibility of decreasing the cell ratio from the conventional values comprised ...