EDN

Synopsys ‘pioneers’ SystemVerilog testbench tool

SANTA CRUZ, Calif. — Synopsys Inc. is bringing the “ecosystem” built around its VCS Verilog simulator to users of third-party simulators with Pioneer-NTB, a SystemVerilog testbench automation tool ...
EDN

SystemVerilog reference verification methodology: RTL

SystemVerilog was designed with language constructs and primitives to help implement the communication between the stimulus and response checking of the testbench, and help manage the expected results ...
Electronic Design

SystemVerilog Gains A Foothold In Verification

SystemVerilog marries a number of verification concepts, primarily in the areas of design, assertions, and testbench creation, that were previously embodied in separate and sometimes proprietary ...
Design-Reuse

SystemC library supporting OVM compliant verification methodology

This paper describes the SystemC library that support Open Verification Methodology as defined by Mentor Graphics and Cadence with their SystemVerilog–based approach. Application of the library in ...
Semiconductor Engineering

Reducing Design Risk With Testbench Acceleration

Part 1 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three ...
Semiconductor Engineering

Updated UVM Cookbook Supports IEEE 1800.2 Standard And Emulation

I’m happy to announce that we at Mentor have just released a fully-updated version of our popular UVM Cookbook, which is available online here. Cookbook Overview Diagram The Universal Verification ...
Electronic Design

EDA> Design And Verification Evolves With SystemVerilog

SystemVerilog is the natural evolution of the Verilog language, extending its capabilities for both design and verification. Demand for this advanced language is clear. Over a dozen EDA companies ...
Design-Reuse

Hardware Co-Verification using VMM HAL-SCEMI On ChipIT Platform

Having SoC for HDTV under verification, verifying different components of SoC at block level are so far satisfactorily done using simulation. Now having full chip level environment and run-ning ...